(1) Field of the Invention
The present invention relates to resin-molded type semiconductor devices, and more particularly to a resin-molded type semiconductor device in which electrodes on a semiconductor chip and inner leads of a lead frame are connected to one another through a tape carrier.
(2) Description of the Related Art
In prior art resin-molded type semiconductor devices, electrode pads of a semiconductor chip and inner leads of a lead frame are respectively connected together via thin metal wires. In such systems, when the number of pins is increased and the pitch of the inner leads is reduced, the wires that have already been wired touch the bonding tool, thus making it difficult to obtain highly reliable bonding. Accordingly, in lieu of such systems, it has become increasingly common to use tape carrier bonding.
A prior art resin-molded type semiconductor device in which tape carrier type bonding is used is shown in FIGS. 1A and 1B. FIG. 1A shows, in plan view, state of the structure before resin molding, and FIG. 1B shows, in sectional view, state of the same after resin molding.
As shown in FIG. 1A, the prior art resin-molded type semiconductor device of this type uses a lead frame 5 which has a central island 7 as a die pad and LF (lead frame) leads 6 extending from its edges toward the island 7. Each of the LF leads 6 has an inner lead portion 6a and an outer lead portion 6b which extends out from the package after the resin molding. The inner lead portions 6a are arranged such that their ends surround the island 7. The island 7 is supported by four suspending pins 8.
As shown in FIGS. 1A and 1B, a semiconductor chip 4 is secured by conductive paste (not shown) or the like to the island 7. Each electrode pad 4a of the semiconductor chip and a corresponding inner lead portion 6a of the lead frame 5 are connected to each other by a copper foil lead 3 supported by a suspender 2d. Specifically, an inner lead portion 3a of the copper foil lead 3 is connected to the associated electrode pad 4a of the semiconductor chip, and an outer lead portion 3b of the copper foil lead 3 is connected to the associated inner lead portion 6a of the lead frame 5. The whole device is molded by molding resin 11.
This resin-molded type semiconductor device of tape carrier type has advantages in that it allows collective bonding and in that it can accommodate multiple pin packaging. It has a further advantage in that a common lead frame can be used for different chip sizes by making common the tape carrier suspender size, i.e., by making the distance L common between outer lead holes.
In this type of prior art semiconductor device, as shown in FIGS. 1A and 1B, the island is not electrically connected to other parts of the device but is held in a floating state (although it is grounded indirectly in the case where the semiconductor chip has a ground electrode formed on the back surface). It has been proposed to provide the lead frame with a pad section or a stage which is grounded for stabilizing electrical characteristics, as disclosed in, for instance, Japanese Patent Application Kokai Publication No. Hei 3-8352 and Japanese Patent Application Kokai Publication No. Hei 4-30541.
In the former case, ground leads of a tape carrier are connected to the pad section of the lead frame. In the latter case, a frame-like power supply plane or ground plane which surrounds the semiconductor chip is provided so that this and the electrode pads of the semiconductor chip are connected via tape carrier leads. Further, in the latter case it is also described that the back surface of the tape carrier is provided with a ground plane which is connected to front surface leads through vias.
As shown, with the resin-molded type semiconductor device of tape carrier type, the single kind of lead frame that is prepared allows packaging of semiconductor chips of different sizes by varying the tape carrier suspender size. In this case, in order to be adapted to be employed in a greater number of different kinds of semiconductor chips, it is necessary to set the suspender size, i.e., the distance between outer lead holes, to be as great as possible.
This means that for packaging of a semiconductor chip having a comparatively small size, each lead frame inner lead and the corresponding semiconductor chip electrode pad are connected to each other by a long copper foil lead. In recent semiconductor devices, the copper foil lead is made finer in width so as to permit structures having an increased number of pins, and this leads to high parasitic inductance and resistance between each outer lead of the package and the associated electrode pad of the semiconductor chip.
By denoting the parasitic inductance and resistance in a power supply circuit and a ground circuit by L and R, respectively, and a change in current flowing into the integrated circuit by .DELTA.I, a corresponding power supply voltage change .DELTA.V is given as: EQU .DELTA.V=L.multidot..DELTA.I/.DELTA.t+R.multidot..DELTA.I
In recent semiconductor integrated circuits, the number of transistors that are switched at a time is on an increasing trend due to scale and versatility increases of the circuits. This means that the current change .DELTA.I is on an increasing trend and becoming sharper due to operation speed increases.
Therefore, when there are high parasitic inductance and resistance in the power supply circuit and the ground circuit, the power supply voltage change .DELTA.V is increased thereby increasing the possibility of erroneous operation in the integrated circuit.
This drawback may be precluded by reducing the inductances and resistances in the power supply circuit and the ground circuit. Doing this, however, is difficult in the prior art semiconductor device because of the copper foil lead trend of becoming finer and longer as described above.
The Japanese Patent Application Kokai Publication No. Hei 3-8352 and the Japanese Patent Application Kokai Publication No. Hei 4-30541 show the connection of a portion of tape carrier copper foil lead to a pad section (i.e., ground conductor) or to a plane for power supply (or ground). By so doing, however, the inductance or resistance cannot be reduced. In the case of using a tape carrier with a ground plane as shown in the Japanese Patent Application Kokai Publication No. Hei 4-30541, it is possible to reduce the inductance and resistance of the ground circuit. However, use of a double side tape carrier requires through-hole plating, and the tape carrier is inevitably expensive. Besides, the inductance and resistance cannot be reduced greatly using this technique.